工作地区：上海
RESPONSIBILITIES:
- Chip level Integration
--Formal Verification
- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
-Develop and enhance entire timing closure flow from frontend(pre-layout) to backend (post-layout) at both chip and block level.
-Develop custom timing scripts using tcl/primetime for clock skewanalysis, special circuits such as clock dividers, core logic <->IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Develop flow to physically partition and floorplan the entire chip.
MINIMUM REQUIREMENTS:
-BSEE, MSEE is preferred
-Project experience in IC design implementation
-Courses taken in circuit design, digital design
-Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) preferred
-Proficient user of Perl or TCL is preferred
工作内容:
-芯片集成，逻辑等价性验证
-芯片物理实现模块划分
-芯片级和模块级时序分析和时序收敛
-高速时钟电路的时序分析和时序收敛
-流程开发,芯片集成，时序分析和时序收敛，模块划分
任职需求:
-电子工程或相关专业硕士生或本科生
-有芯片设计经验
-有相关课程背景：电路设计，数字电路
-有相关EDA工具使用经验：Synopsys (DC/PT/Formality), Cadence (LEC)
-具有脚本编写能力者优先：Perl， TCL